It & Software Online Course by Udemy, On Sale Here
Using Verilog and Vivado Design Suite
An excellent training about Hardware
Getting Started with Custom AXI peripherals for Zynq Devices
Sometimes the IP’s and the peripheral resources available with Zynq devices are not enough to match performance, functionality requirements which are growing day by day. This opens up a door to develop a custom peripheral / Core / Hardware accelerator with Verilog RTL and integrate them with ZYNQ device with World popular Industry defacto standard viz. AXI Interface. This course will cover steps to build up AXI lite and AXI stream interfaces onto RTL to quickly build Cores ready to communicate with ZYNQ. Welcome to Part 2 of the Embedded Design Series with Zynq FPGA’s and Vivado.
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