FPGA Design with High Level Synthesis Tool (VIVADO HLS) | Hardware Online Course by Udemy

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Design, Simulate, Synthesize & Export IP with VIVADO HLS (High Level Synthesis) : An FPGA Design Approach with C/C++

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FPGA Design with High Level Synthesis Tool (VIVADO HLS)

Learn from Basic HLS Design & C-Simulation to Design Computer Vision Application [Real Time Sobel Edge Detection]High Level Synthesis is new approach on FPGADesign with C/C++ Language. This Course covers: Creatingnew project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project’s which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Exporting HLS Design in to IP core Format to VIVADO IP Integrator. We also have include session on “Sobel Edge IP design in HLS, exporting it to VIVADO tool and then implementing/testing it on Zybo FPGA”. After Completing this course you will be able to Design, Simulate, Synthesize and Implement/Export HLSprojects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL. In this Lab you are going to do lab on Design, Simulation, Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator(NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.

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