FPGA Design Learning VHDL | Hardware Online Course by Udemy

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From zero to VHDL designer. Learn how to implement your VHDL design on FPGA starting from scratch

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FPGA Design Learning VHDL

UPDATE 2020, Jan-09: add quiz in section 32018,April-08: Added quizzes on section2, updated caption up to lesson 10 How many times doyouwaste your time in finding some examples useful to resolve your VHDL problems and didn’t get anything useful?YES, it is true that we can find a lot of information for free, but not all the information we get is good stuff. Many times we need a huge amount of time to filter good stuff from useless material. Even if we get the information for free, we often don’t think about the time we are wasting and to the “equivalent money” we are losing wasting this time. In Surf-VHDL, we have more than 20 years in the FPGA/ASIC VHDL design. In this course, you will learn the basic rules to implement and efficient hardware design and how to apply these rules using VHDL. Here what you will learn at the end of the course: Entity / Architecture pair definitionConcurrencyVHDL Coding Style: Structural, Behavioral, SequentialEvent and TransactionDelay Modeling: Inertial vs Transport delayConcurrent Conditional Signal AssignmentUnderstanding Driver & Source conceptParametric Design: GenericsVHDL Types and Data objectVHDL Types of Data Object: Signal, Variable, Constant and FILEType bit vs ulogic vs std logicSigned and Unsigned Data TypesType Conversion and Type CastingSubtype definitionProcess StatementSequential Conditional Statement: IF and CASESequential-Iterative Statement: FOR and WHILEThe Assert StatementSequential WAIT StatementSensitivity List vs WAIT StatementProcedure and FunctionPackagesConcurrent iterative Statement FOR GENERATEConcurrent conditional Statement IF GENERATETextIO package: Read/Write from fileTest bench design and simulationThe most important section is the LAB section. This is the real value of this course. In the LAB section, you will learn how to implement Heart-bit design: let’s start with a blinking ledSeven segment display: write a VHDL code and drive a seven-segment displayUART: learn how to implement a UART 16650 compatible with internal FIFOCommand Parser: VHDL design that contains the LABs above. Connect your board to a PC and start to communicate with it. All the LABs are provided with the VHDL code that you have to complete and simulate. In the LAB videos, there will be addressed the exercise solution: you will learn how to implement the lab VHDL code, simulate and layout on FPGA Enjoy the course and start becoming a VHDL designer!

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