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Learn how things got started in VLSI
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VSD – Circuit Design & SPICE Simulations – Part 1
So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis. OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk, But, sit back, and give it a thought “Have you done it all?” “Did you know, where does the delay of a cell actually comes from?” “We have learnt about delay models, but are the models accurate?” “How do you verify, if what you are doing in static timing analysis, is correct?” and many more. These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own. And, here’s the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst So let’s get started and keep those questions coming in the forum, and I will answer all of them. See you in class!
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